#define MEM0_OFFSET(dspAddress) ((dspAddress)&~(~0<<22))
#define MEM0_PAGE(dspAddress) ((dspAddress)>>22)

#define MEM1_WINDOW_BASE 0x01800000
#define MEM1_OFFSET(dspAddress) ((dspAddress)-MEM1_WINDOW_BASE)

/* emif and Co */
#define DSP_EMIF_GCTL     MEM1_OFFSET(0x01800000)
#define DSP_EMIF_CE1      MEM1_OFFSET(0x01800004)
#define DSP_EMIF_CE0      MEM1_OFFSET(0x01800008)
#define DSP_EMIF_CE2      MEM1_OFFSET(0x01800010)
#define DSP_EMIF_CE3      MEM1_OFFSET(0x01800014)
#define DSP_EMIF_SDRAMCTL MEM1_OFFSET(0x01800018)
#define DSP_EMIF_SDRAMREF MEM1_OFFSET(0x0180001c)

/* controle */
#define DSP_HSR    MEM1_OFFSET(0x01A7FFF0)
#define DSP_HSR_INTSRC  (1<<0)   /*1 decale de 0*/
#define DSP_HSR_INTAVAL (1<<1)
#define DSP_HSR_INTAM   (1<<2)
#define DSP_HSR_CFGERR  (1<<3)
#define DSP_HSR_EEREAD  (1<<4)

#define DSP_HDCR   MEM1_OFFSET(0x01A7FFF4)
#define DSP_HDCR_WARMRESET (1<<0)
#define DSP_HDCR_DSPINT    (1<<1)
#define DSP_HDCR_PCIBOOT   (1<<2)

#define DSP_DSPP   MEM1_OFFSET(0x01A7FFF8)
#define DSP_DSPP_PAGE (~((~0)<<10))
#define DSP_DSPP_PAGE_SET(r,v) do{r&=~DSP_DSPP_PAGE; r|= v & DSP_DSPP_PAGE }while(0)
#define DSP_DSPP_PAGE_GET(r) ((r)&DSP_DSPP_PAGE)
#define DSP_DSPP_MAP (1<<10)

/*
0x00000010 0xffc00008 0x00400000
0x00000014 0xff800000 0x00800000
0x00000018 0xfffffff1 0x00000010
*/